As faster operation of computer systems has been sought, numerous hardware/firmware features have been employed to achieve that purpose. One feature widely incorporated in central processing units (CPUs) that is directed to increasing the speed of operation is pipelining in which the various stages of execution of a series of consecutive machine level instructions are undertaken simultaneously. For example, during a given time increment, a first stage of a fourth (in order of execution) instruction may be undertaken while a second stage of a third instruction, a third stage of a second instruction and a fourth stage of a first instruction are all undertaken simultaneously. This procedure dramatically increases the speed of operation of a CPU.
The execution of the instructions in the repertoire of instructions of a CPU requires the coordinated sequential generation of numerous control signals, and these control signal combinations are particularly complex and diverse in a pipelined CPU. The control signals are typically derived from firmware stored in a read-only-memory (ROM). This firmware consists of stored control words, each control word representing a combination of binary signals, or bits, necessary to carry out a microstep in the execution of one or more instructions.
In the CPU family in which the subject invention finds exemplary use, a virtual control word set, or control program, of on the order of 4K words of 256 bits each is required to provide for all the necessary signal combinations for performing the numerous microsteps during execution of the instruction set of the CPU. This CPU family is implemented in very large scale integrated (VLSI) circuitry on several chips including an address and execution (AX) chip which incorporates the ROM containing the control word set. However, those skilled in the art will understand that, at the state of the art, a ROM of 4K by 256 bits would take up much of the room available for circuitry on a VLSI chip. Since the remainder of the AX chip is itself very complex, a ROM of this size cannot be accommodated, and this constraint presented a serious problem which was successfully addressed by the use of the present invention. Further, in combination with other innovations, a very significant additional decrease in the size of the control store ROM for the AX chip was achieved.